Computer Science at U.C. Berkeley. In July 2000 he joined the Cadence Berkeley Laboratories where he continues to work on synthesis and verification problems. Since July 2002, he is also adjunct professor at the University of California at Berkeley. In 2003 Andreas was awarded IEEE Fellow. In August 2003 Andreas became the Director of Cadence Laboratories and was also promoted to Cadence Fellow in 2004.

内容摘要：

The raise from gate-level to RTL design entry was driven by the need for higher design productivity. Specifically, RTL modeling allowed faster functional simulation and thus addressed the need for higher verification capacity to verify the growing system complexity. Furthermore, the availability of static timing analysis, formal equivalence checking between RTL and gate level, and automatic logic synthesis from RTL to gates supported a predictable automated implementation flow. The need for system-level modeling has similar motivations, mostly faster simulation for supporting early system validation and software development. However, there are significant differences. First, the level of abstraction needed for fast performance is significantly higher which results in a number of challenges for a consistent implementation flow. Second, there is no uniform level of model abstraction as large system models require a fine-tuned balance between modeling detail and performance for the different components. In this talk, we will provide an overview of the challenges in system level design and discuss a number of technologies that are currently available and under development.